Experimental study of the influence of pipelining on performance and hardware costs of Hamming error-correcting code algorithm

Objective. The paper investigates the impact of pipelining on the efficiency of Hamming code implementation in FPGA devices. Pipelining is considered as a method to increase the speed of operation for modules implementing error-correcting algorithms.
Method. An empirical analysis was conducted to evaluate both the performance speed and hardware requirements of various implementations of Hamming codes on FPGAs. During this study, attention was given to resources consumed by the FPGA and the maximum clock frequency at which the module operates correctly.
Result. Pipelining has significantly optimized the implementation of Hamming codes.
Conclusion. Pipelining proves to be an effective optimization technique when properly selecting pipeline depth for the Hamming code realization.

1. Hasija T., et al. A survey on performance analysis of different architectures of AES algorithm on FPGA. Modern Electronics Devices and Communication Systems: Select Proceedings of MEDCOM 2021. 2023;39-54.

2. Kumar T.M., et al. A low area high speed FPGA implementation of AES architecture for cryptography application. Electronics. 2021; 10(16):2023.

3. Kreowsky P., Stabernack B. A full-featured FPGA-based pipelined architecture for SIFT extraction. IEEE Access. 2021; 9:128564-128573

4. Dashkevich E.A. Features of architectures and operating modes of modern microprocessors. Bulletin of Science and Education. 2018; 2(5 (41):37-39. (In Russ)

5. Konstantopoulou E., Athanasiou G., Sklavos N. Review and Analysis of FPGA and ASIC Implementations of NIST Lightweight Cryptography Finalists. ACM Computing Surveys. 2025; 57(10):1-35.

6. Tarasov I.E., Lyulyava D. V. Design of Pipelined Computing Devices with Consideration of Topological Representation. (In Russ)

7. Kobaylo A.S. Architectural Features of Real-Time Computing Systems. Integrated Pipelined Computers. Proceedings of BSTU. Series3:Physical and Mathematical Sciences and Informatics. 2017;9(200):129-132.

8. Kostyukov A.S., et al. Error-Resistant Coding in Modern Communication Formats. Bulletin of Voronezh State Technical University. 2019;15( 2):132-138. (In Russ)

9. Hailes P., et al. A survey of FPGA-based LDPC decoders. IEEE Communications Surveys & Tutorials. 2015; 18(2):1098-1122.

10. Khan S.A., et al. Protocols and mechanisms to recover failed packets in wireless networks: History and evolution. IEEE Access. 2016; 4: 4207-4224.

11. Zolotaryov V.V., Ovechkin G.V. Error-Resistant Coding. Methods and Algorithms. Reference Book. – Moscow: Goryachaya Liniya–Telecom, 2004. (In Russ)

12. Almazrouei K., Alnajjar K.A. Error-correcting Codes in Communication Systems. 2024 International Wireless Communications and Mobile Computing (IWCMC). 2024;1-6.

13. Sabbry N.H., Levina A. Hamming code: An analysis of its reliability and efficiency in computer networks. 2023 International Conference Automatics and Informatics (ICAI). IEEE, 2023: 356-361.

14. Aliev Y., Ivanova G., Borodzhieva A. Design and Development of Interactive Software Models for Teaching Coding Theory: A Case Study on Hamming Codes—General Algorithm. Applied Sciences. 2025;15(8):4231.

15. Efanov D.V., Blyudov A.A. Hamming Codes and Their Detecting Capabilities in Functional Control Circuits. Informatics and Control Systems. 2012; 2:100-111. (In Russ)

16. Umapathy K., et al.FPGA based implementation of hamming encoder and decoder. Micro-Electronics and Telecommunication Engineering:Proceedings of 4th ICMETE 2020.Singapore:Springer Singapore, 2021:245-251.

17. YosysHQ. Yosys Open SYnthesis Suite [Electronic resource]. – 2025. – Access mode: https://yosys.readthedocs.io/_/downloads/en/latest/pdf/ (date of request: 09.10.2025).

18. Jafarof N., Kent K.B. Enhancing the VTR Flow: Integration of ABC9 via Yosys for Better Technology Mapping and Optimization. 2024 International Workshop on Rapid System Prototyping (RSP). IEEE, 2024:. 56-62.

19. Gavrilov S.V., et al. Development of Trusted Design Tools for Integrated Circuits Based on Heterogeneous FPGAs. Proceedings of the Institute for System Programming of the Russian Academy of Sciences. 2023; 35(5): 107-126. (In Russ)

20. Kamkin A.S., et al. Comparison of High-Level Synthesis and Digital Hardware Design Tools. Proceedings of the Institute for System Programming of RAS. 2022; 34(5):7-22. (In Russ)

21. Chochaev R.Zh., et al. Models and Methods for Analyzing the Structure of FPGA Switching Resources: A Review. News of Higher Education Institutions. Electronics. 2020; 25(5):410-422. (In Russ)

22. McLoone M., McCanny J.V. Rijndael FPGA implementations utilising look-up tables. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology. 2003; 34( 3):261-275.

23. YosysHQ/nextpnr: nextpnr portable FPGA place and route tool [Electronic resource]. – 2025. – Access mode: https://github.com/YosysHQ/nextpnr (date of request: 15.09.2025).