vdgtuВестник Дагестанского государственного технического университета. Технические наукиHerald of Dagestan State Technical University. Technical Sciences2073-61852542-095XDaghestan State Technical University10.21822/2073-6185-2024-51-3-60-71vdgtu-1556Research ArticleИНФОРМАЦИОННЫЕ ТЕХНОЛОГИИ И ТЕЛЕКОММУНИКАЦИИINFORMATION TECHNOLOGY AND TELECOMMUNICATIONSТехнологии кеширования данных в современных микропроцессорахData caching technologies in modern microprocessorsЕгуновВ. А.EgunovV. A.

Егунов Виталий Алексеевич, кандидат технических наук, доцент, кафедра ЭВМ и систем 

400005, г. Волгоград, пр. им. Ленина, 28 

Vitaly A. Egunov, Cand. Sci. (Eng), Assoc.Prof., Computers and Systems Department 

28 Lenin Ave., Volgograd 400005 

vegunov@mail.ruШабаловскийВ. А.ShabalovskyV. A.

Шабаловский Владимир Андреевич, магистрант, кафедра ЭВМ и систем 

400005, г. Волгоград, пр. им. Ленина, 28 

Vladimir A. Shabalovsky, Master Student, Computers and Systems Department 

28 Lenin Ave., Volgograd 400005 

shabalovsky.v@mail.ruВолгоградский государственный технический университетРоссияVolgograd State Technical UniversityRussian Federation2024021020245136071Copyright © Егунов В.А., Шабаловский В.А., 20242024Егунов В.А., Шабаловский В.А.Egunov V.A., Shabalovsky V.A.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://vestnik.dgtu.ru/jour/article/view/1556

Цель. Исследование, представленное в статье, направлено на изучение методов повышения эффективности программного обеспечения в современных вычислительных системах с иерархической структурой памяти. Метод. Исследование основано на технологиях кеширования данных в микропроцессорах. Результат. Представлены результаты анализа различных подходов к разработке эффективного программного обеспечения с учетом характеристик подсистемы памяти вычислительной системы, что позволило доказать важность кеш-памяти в улучшении производительности и взаимодействии компонентов компьютера. Вывод. Кеш-память является критически важным элементом в архитектуре микропроцессоров, играющим ключевую роль в определении производительности вычислительной системы. Оптимизация использования кеша может заметно улучшить время доступа к данным и, как следствие, общую производительность системы. Разработчикам программного обеспечения необходимо уделять особое внимание характеристикам подсистемы памяти при проектировании и реализации решений.

Objective. The study presented in the paper is aimed at studying the methods for improving the efficiency of software in modern computing systems with a hierarchical memory structure. Method. The study is based on data caching technologies in microprocessors. Result. The article presents the results of the analysis of various approaches to the development of efficient software taking into account the characteristics of the memory subsystem of the computing system, which made it possible to prove the importance of cache memory in improving the performance and interaction of computer components. Conclusion. Cache memory is a critical element in the architecture of microprocessors, playing a key role in determining the performance of the computing system. Optimizing the use of cache can significantly improve data access time and, as a result, overall system performance. Software developers need to pay special attention to the characteristics of the memory subsystem when designing and implementing solutions.

кеш-памятьоптимизацияэффективность программного обеспечениякеш-промахкеш-попаданиеассоциативность кеш-памятиcache memoryoptimizationsoftware efficiencycache misscache hitassociativity of cache memoryReferencesBhat, Subrahmanya and Bhat, Subrahmanya and Kamath, K. R, Cache Hierarchy in Modern Processors and Its Impact on Computing (May 11, 2017). International Journal of Management, IT and Engineering (IJMIE), Volume 5, Issue 7, pp. 248-253, ISSN: 2249-0558, July 2015, Proceedings of National Conference “Recent Advances in IT, Management and Social Sciences”, Manegma – 2015, Mangalore on 23rd April, 2015, ISBN No. 978-81-929306-6-4, Available at SSRN: https://ssrn.com/abstract=2966616Bhat, Subrahmanya and Bhat, Subrahmanya and Kamath, K. R, Cache Hierarchy in Modern Processors and Its Impact on Computing (May 11, 2017). International Journal of Management, IT and Engineering (IJMIE), Volume 5, Issue 7, Pp. 248-253, ISSN: 2249-0558, July 2015, Proceedings of National Conference “Recent Advances in IT, Management and Social Sciences”, Manegma – 2015, Mangalore on 23rd April, 2015, ISBN No. 978-81-929306-6-4, Available at SSRN: https://ssrn.com/abstract=2966616Alexander von Bülow, Jürgen Stohr, and Georg Färber Towards an Efficient Use of Caches in State of the Art Processors for Real-Time Systems // Work-In-Progress Session of the 16th Euromicro Conference on Real-Time Systems. — Catania, Italy:Steve Goddard, 2004. — С. 5-9.Alexander von Bülow, Jürgen Stohr, and Georg Färber Towards an Efficient Use of Caches in State of the Art Processors for Real-Time Systems. Work-In-Progress Session of the 16th Euromicro Conference on Real-Time Systems. Catania, Italy:Steve Goddard, 2004;5-9.Cortex-A5 // developer.arm URL: https://developer.arm.com/Processors/Cortex-A5Cortex-A5. developer.arm URL: https://developer.arm.com/Processors/Cortex-A5Processeurs Intel® Core™ de 14ᵉ génération pour PC de bureau // intel.fr URL: https://www.intel.fr/content/www/fr/fr/products/docs/processors/core/core-14th-gen-desktop-brief.htmlProcesseurs Intel® Core™ de 14ᵉ génération pour PC de bureau // intel.fr URL: https://www.intel.fr/content/www/fr/fr/products/docs/processors/core/core-14th-gen-desktop-brief.htmlАнтонов А.А., Ключев А.О., Комар М.С., Кустарев П.В., Кучерявый Е.А., Молчанов Д.А., Петров В.И., Платунов А.Е. Разработка протокола множественного доступа для процессоров с многоуровневым кэшированием // Научно-технический вестник информационных технологий, механики и оптики. 2015. №3. URL: https://cyberleninka.ru/article/n/razrabotka-protokola-mnozhestvennogo-dostupadlya-protsessorov-s-mnogourovnevym-keshirovaniem.Antonov A.A., Klyuchev A.O., Komar M.S., Kustarev P.V., Kucheryavyj E.A., Molchanov D.A., Petrov V.I., Platunov A.E. Development of a multiple access protocol for processors with multi-level caching // Scientific and Technical Bulletin of Information Technologies, Mechanics and Optics. 2015;3. URL: https://cyberleninka.ru/article/n/razrabotka-protokola-mnozhestvennogo-dostupa-dlya-protsessorov-smnogourovnevym-keshirovaniem. (In Russ)Measuring the size of the cache line empirically // lemire URL: https://lemire.me/blog/2023/12/12/measuring-the-size-of-the-cache-line-empirically/Measuring the size of the cache line empirically // lemire URL: https://lemire.me/blog/2023/12/12/measuring-the-size-of-the-cache-line-empirically/Bruce Jacob, Spencer W. Ng, David T. Wang, CHAPTER 1 - An Overview of Cache Principles, Editor(s): Memory Systems,Morgan Kaufmann, 2008, Pages 57-77, ISBN 9780123797513.Bruce Jacob, Spencer W. Ng, David T. Wang, CHAPTER 1 - An Overview of Cache Principles, Editor(s): Memory Systems,Morgan Kaufmann, 2008, Pages 57-77, ISBN 9780123797513.Eze, Val & Eze, Martin & Edozie, Enerst & Eze, Esther. (2023). Design and Development of Effective Multi-Level Cache Memory Model. International Journal of Recent Technology and Applied Science (IJORTAS). 5. 54-64. 10.36079/lamintang.ijortas-0502.515.Eze, Val & Eze, Martin & Edozie, Enerst & Eze, Esther. (2023). Design and Development of Effective Multi-Level Cache Memory Model. International Journal of Recent Technology and Applied Science (IJORTAS). 5. 54-64. 10.36079/lamintang.ijortas-0502.515.IBM's New System Z CPU Offers 40 Percent More Performance per Socket, Integrated AI // extremetech URL: https://www.extremetech.com/computing/326402-ibms-new-system-z-cpu-offers-40-percent-moreperformance-per-socket-integrated-aiIBM's New System Z CPU Offers 40 Percent More Performance per Socket, Integrated AI // extremetech URL: https://www.extremetech.com/computing/326402-ibms-new-system-z-cpu-offers-40-percent-moreperformance-per-socket-integrated-aiCache Memory in Computer Organization // geeksforgeeks URL: https://www.geeksforgeeks.org/cachememory-in-computer-organization/.Cache Memory in Computer Organization // geeksforgeeks URL: https://www.geeksforgeeks.org/cachememory-in-computer-organization/.Jouppi, Norman. (1998). Improving Direct-Mapped Cache Performance by the Addition of a Small FullyAssociative Cache Prefetch Buffers.. Conference Proceedings - Annual Symposium on Computer Architecture. 18. 388-397. 10.1109/ISCA.1990.134547.Jouppi, Norman. (1998). Improving Direct-Mapped Cache Performance by the Addition of a Small FullyAssociative Cache Prefetch Buffers.. Conference Proceedings - Annual Symposium on Computer Architecture. 18. 388-397. 10.1109/ISCA.1990.134547.Garzón, Esteban & Hanhan, Robert & Lanuzza, Marco & Teman, Adam & Yavits, Leonid. (2024). FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access. PP. 10.1109/ACCESS.2024.3355961.Garzón, Esteban & Hanhan, Robert & Lanuzza, Marco & Teman, Adam & Yavits, Leonid. (2024). FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access. PP. 10.1109/ACCESS.2024.3355961.Guocong Quan, Atilla Eryilmaz, Jian Tan, Ness Shroff,Prefetching and caching for minimizing service costs: Optimal and approximation strategies, Performance Evaluation, 2021;145:102149, ISSN 0166-5316,Guocong Quan, Atilla Eryilmaz, Jian Tan, Ness Shroff. Prefetching and caching for minimizing service costs: Optimal and approximation strategies, Performance Evaluation, 2021;145:102149, ISSN 0166-5316Function core::arch::x86_64::_mm_prefetch // doc.rust-lang URL: https://doc.rust-lang.org/beta/core/arch/x86_64/fn._mm_prefetch.html.Function core::arch::x86_64::_mm_prefetch //doc.rust-lang URL: https://doc.rustlang.org/beta/core/arch/x86_64/fn._mm_prefetch.html.Филисов Д.А. Стратегии оптимизации для высоконагруженныхприложений: повышение общей производительности // Вестник науки. 2023. №7: https://cyberleninka.ru/article/n/strategii-optimizatsiidlya-vysokonagruzhennyh-prilozheniy-povyshenie-obschey-proizvoditelnosti.Filisov D.A. Optimization strategies for high-load applications: improving overall performance // Bulletin of Science. 2023. №7 https://cyberleninka.ru/article/n/strategii-optimizatsii-dlya-vysokonagruzhennyhprilozheniy-povyshenie-obschey-proizvoditelnosti. (In Russ)Wu, HT., Cho, HH., Wang, SJ. et al. Intelligent data cache based on content popularity and user location for Content Centric Networks. Hum. Cent. Comput. Inf. Sci. 2019;(9)44. https://doi.org/10.1186/s13673-019-0206-5.Wu, HT., Cho, HH., Wang, SJ. et al. Intelligent data cache based on content popularity and user location for Content Centric Networks. Hum. Cent. Comput. Inf. Sci. 9, 44 (2019). https://doi.org/10.1186/s13673-019-0206-5.Аль-згуль Мосаб Басам Гибридные алгоритмы в системах кэширования объектов // Advanced Engineering Research (Rostov-on-Don). 2008. №4-39. URL: https://cyberleninka.ru/article/n/gibridnyealgoritmy-v-sistemah-keshirovaniya-obektov.Al'-zgul' Mosab Basam. Hybrid algorithms in object caching systems. Advanced Engineering Research (Rostov-on-Don). 2008. №4-39. URL: https://cyberleninka.ru/article/n/gibridnye-algoritmy-v-sistemahkeshirovaniya-obektov. (In Russ)Locality of Reference and Cache Operation in Cache Memory // turbopages URL: https://www.geeksforgeeks.org/ ocality-of-reference-and-cache-operation-in-cache-memory/.Locality of Reference and Cache Operation in Cache Memory//turbopages URL: https://www.geeksforgeeks.org/locality-of-reference-and-cache-operation-in-cache-memory/.Юрушкин М. В., Семионов С. Г. Переразмещение матриц к блочному виду с минимизацией использования дополнительной памяти // Известия вузов. Северо-Кавказский регион. Серия: Технические науки. 2017. №3 (195). URL: https://cyberleninka.ru/article/n/pererazmeschenie-matrits-k-blochnomuvidu-s-minimizatsiey-ispolzovaniya-dopolnitelnoy-pamyati.YUrushkin M. V., Semionov S. G. Repositioning matrices to a block view while minimizing the use of additional memory . News of universities. The North Caucasus region. Series: Technical Sciences. 2017. №3 (195). URL: https://cyberleninka.ru/article/n/pererazmeschenie-matrits-k-blochnomu-vidu-s-minimizatsieyispolzovaniya-dopolnitelnoy-pamyati. (In Russ)LRU Cache — A Cache Data Structure // medium URL: https://ogroetz.medium.com/lru-cache-a-cachedata-structure-1fab0d948e94.LRU Cache — A Cache Data Structure // medium URL: https://ogroetz.medium.com/lru-cache-a-cachedata-structure-1fab0d948e94.GCC, the GNU Compiler Collection // gcc.gnu URL: https://gcc.gnu.org/.GCC, the GNU Compiler Collection // gcc.gnu URL: https://gcc.gnu.org/.Chapter 25. Profiling memory accesses with perf mem // access.redhat URL: https://access.redhat.com/documentation/enus/red_hat_enterprise_linux/8/html/monitoring_and_managing_system_status_and_performance/Chapter 25. Profiling memory accesses with perf mem//access.redhat URL: https://access.redhat.com/documentation/enus/red_hat_enterprise_linux/8/html/monitoring_and_managing_system_status_and_performance/Егунов В.А. Кэш-оптимизация процесса вычисления собственных значений на параллельных вычислительных системах// Прикаспийский журнал: управление и высокие технологии. - 2019. - № 1 (45). - C. 154-163.Egunov V.A. Cache optimization of the process of calculating eigenvalues on parallel computing systems. Caspian Journal: Management and High Technologies. 2019;1 (45):154-163. (In Russ)Егунов В.А. О влиянии кэш-памяти на эффективность программной реализации базовых операций линейной алгебры // Прикаспийский журнал: управление и высокие технологии. - 2018. - № 3. - C. 88-96.Egunov V.A. On the effect of cache memory on the effectiveness of software implementation of basic linear algebra operations. Caspian Journal: Management and High Technologies. 2018;3: 88-96.Егунов, В.А. Метод улучшения стратегии кеширования для вычислительных систем с общей памятью / В.А. Егунов, А.Г. Кравец // Программная инженерия. - 2023. - Т. 14, № 7. - C. 329-338. - DOI: 10.17587/prin.14.329-338.Egunov V.A., Kravec A.G. A method for improving the caching strategy for computing systems with shared memory. Software Engineering. 2023; 14(7):329-338. - DOI: 10.17587/prin.14.329-338. (In Russ)Kravec A.G., Egunov V.A. The Software Cache Optimization-Based Method for Decreasing Energy Consumption of Computational Clusters// Energies. 2022;15(20):16 (October-2) [Special issue «Smart Energy and Sustainable Environment»]. Article 7509. 16p. DOI: https://doi.org/10.3390/en15207509.Kravec A.G., Egunov V.A. The Software Cache Optimization-Based Method for Decreasing Energy Consumption of Computational Clusters. Energies. 2022;15(20):16 (October-2) [Special issue «Smart Energy and Sustainable Environment»]. Article 7509. DOI: https://doi.org/10.3390/en15207509. (In Russ)

The authors declare that there are no conflicts of interest present.